The present invention relates to semiconductor substrates, and more particularly, to methods and semiconductor structures having a release layer for controlling cracks that form during dicing or as a result of package-induced stresses.
Integrated circuits are fabricated by building multiple layers of wiring and passivation on substrates (wafers) that contain semiconductor devices. Upon completion of substrate-level processing, wafers are diced to provide individual chips. The dicing process often causes cracks that damage active areas of the chips. To prevent such damage, crack stop layers have been employed along the perimeter of the chip.
These crack stop layers often take on additional functions for low-K dielectrics, such as providing an edge seal to prevent moisture ingress that can damage or destroy active areas of a chip. They also protect active areas of chips from cracks, which may emanate from the diced edges as a result of package-induced stresses. However, as the dielectric constant of the material is lowered, the insulator material becomes mechanically weaker, and as such, it becomes significantly easier for the crack stop/edge seal to be breached. To address this problem, prior art has been focused on the use of multiple redundant crack stop/edge seals. However, this type of conventional approach takes up valuable “real estate” on the chip, ultimately reducing the number of chips that can be produced per wafer.
Thus, as retention of real estate on the chip is crucial for productivity, further improved methods and processing layers are needed in the art for controlling edge-cracking in chips. Preferably, these methods and layers would take up minimal space on the chip and allow for the control of cracking during dicing, as well as in service.